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| (R) CB35000 SERIES HCMOS STANDARD CELLS PRELIMINARY DATA FEATURES s s s s s s s 0.5 micron triple layer metal HCMOS5S process featuring retrograde well technology, low resistance salicided active areas, polysilicide gates and thin metal oxide. 3.3 V optimized transistor with 5 V I/O interface capability 2 - input NAND delay of 210 ps (typ) with fanout = 2. Broad I/O functionality including LVCMOS, LVTTL, GTL, PECL, and LVDS. High drive I/O; capability of sinking up to 48 mA with slew rate control, current spike suppression and impedance matching. Generators to support SPRAM, DPRAM, ROM and MULT with BIST options. Extensive embedded function library including DSP and ST micros, popular third party micros and Synopsys synthetic libraries. s s s s s s s s s s s s Fully independent power and ground configurations for inputs, core and outputs. I/O ring capability up to 800 pads. Output buffers capable of driving ISA, EISA, PCI, MCA, and SCSI interface levels. Active pull up and pull down devices. Buskeeper I/O functions. Oscillators for wide frequency spectrum. Broad range of 300 SSI cells. Low Power / Low Drive library subset. Design For Test includes IEEE 1149.1 JTAG Boundary Scan architecture built in. Cadence and Mentor based design system with interfaces from multiple workstations. Broad ceramic and plastic package range. Latchup trigger current > +/- 500 mA. ESD protection > +/- 4000 volts. Table 1 Module Generator Library Description 256K bits max 16K word max 64 bit max Zero static current Tristate outputs 128K bits max 8K word max 64 bit max Zero static current Tristate outputs 2M bits max 32K word max 64 bit max Diffusion programmable Tristate outputs Parallel asynchronous operation 2's complement product 6 to 64 bits for both inputs Ripple Carry or Fast Carry Look Ahead 1/16 Cell SPRAM DPRAM ROM MULT July 1995 CB35000 SERIES GENERAL DISCRIPTION The CB35000 standard cell series uses a high performance, low voltage, triple level metal, HCMOS5S 0.5 micron process to achieve subnanosecond internal speeds while offering very low power dissipation and high noise immunity. With an average gate density of 5500 gates/mm2, the CB35000 family allows the design of highly complex devices. The potential available gate count ranges above 1.5 Million equivalent gates. Devices can operate over a Vdd voltage range of 2.7 to 3.6 volts. The I/O count for this array family ranges to over 600 signals and 800 pins dependent upon the package technology utilized. A Sea of I/O approach has been followed to give a solution to Figure 1 Advantages of stacked contacts and vias today's problems of drive levels and specialized interface standards. The technology does not utilize a set bond pad spacing but allows for pad spacings from 80 microns upwards. The I/O is fully compatible with that of the ISB35000 Structured Array family. The I/O can be configured for circuits ranging from low voltage CMOS and TTL to 350 mHz plus low swing differential circuits. Standards like GTL, SCSI-2, 3.3 Volt PCI, CTI, and a limited set of 5.0 Volt interfaces are currently being addressed. A specialized set of impedance matched transmission line driver LVTTL type circuits are also available with 25, 35, 45, and 55 Ohm output impedance. These buffers sacrifice direct current capabilities for matching positive and negative voltage and current waveforms. CONVENTIONAL VIA LAYOUT STACKED VIA LAYOUT 2nd VIA METAL 3 1st VIA METAL 2 CONTACT METAL 1 GATE 1st DIELECTRIC 3rd DIELECTRIC CONTACT / VIA PLUGS 2nd DIELECTRIC ISOLATION SUBSTRATE AREA SAVINGS UP TO 20% FOR RANDOM LOGIC SIMPLIFIED ROUTING AND DESIGN RULE CHECKING 2/16 (R) CB35000 SERIES LIBRARY OVERVIEW The design of the CB35000 family has been optimized to allow extremely high density, high speed and low power designs. For these reasons a wide range of cells with different ranges of driving capability are available in the library. The library cells have been optimized in term of functional and electrical parameters in order to have: s Good balancing s Maximum speed s Optimum Threshold voltage s Symmetric Vdd/Vss Noise margin s Minimum Power-Speed figure Surrounding the core are configurational specialized transistors forming a Sea of I/O giving a high degree of flexibility to the system designer. The geometrical aspect of the cells was configured to allow extremely dense design, fully exploiting the features of the Place and Route tool in terms of horizontal and vertical routing grids. For Place and Route, three levels of metal are utilized. Intracell and intercell wiring are limited to first metal, with second and third metal levels dedicated to interconnect wiring and power distribution. Each cell gives the possibility to use 10 horizontal wiring channels using third metal. With the horizontal grid unit being the same as the Metal 2 minimum contacted pitch, the vertical wiring can be done on every grid point, without limitation. TECHNOLOGY OVERVIEW A major feature of the HCMOS5S process is salicided active areas. This results in source drain areas that are of one to two ohms resistance as opposed to the hundreds or thousands of ohms of source drain resistance in previous technologies. This very low resistance is one reason that very low transistor widths could be utilized in the cell design since drive is not lost due to source drain resistance. This use of low width transistors results in lower capacitance loading of the gates due to the smaller areas utilized. Low resistance, low capacitance, and small gates results in low power usage for inverters as compared to previous technologies. The reduction in power consumption allows the usage of salicided active stripes to distribute power internally to the simple cell, replacing, in some cases, the usage of the first metal layer. This saves silicon area by allowing greater density, permeability and routability of the cells resulting in greater overall circuit density. The standard power distributions are Internal Vdd and Vss, serving the internal cells and the prebuffer sections of the I/O, External Vdd and Vss serving the output transistors only, and Receiver Vdd and Vss serving the first stages of the receiver cells. Optional distributions for 5.0V interface, GTL, CTL, and other standards can be utilized as necessary. 10 Em Figure 2. ND2 Core Cell 3/16 (R) CB35000 SERIES LIBRARY The following section details the elements which make up the CB35000 Series library. The elements are organized into three categories: 1. Macrocell library with Input, Output, Bidirectional Buffers including JTAG macrocells and Core cells. 2. Macrofunctions 3. Module generators. I/O BUFFERS CB35000 technology does not utilize a standard type I/O cell but is a leader in the emerging Sea of I/O approach to handling the chip interface problem. This approach starts at the bond pad area of the I/O where the pad size and pitch is not determined until the customers choice of packaging, signal interface standards and I/O count is considered. Wire bond pad spacings for 80 micron centres are available where large signal counts are most important. Pad spacing can be increased incrementally. It is expected that most designs will use 100 micron spacings or above. It is also possible to use different spacings for different width output sections when needed within the same device. Along with the variable bond pad spacing the I/O output transistor section does not have a fixed width. Previous technologies utilized a design approach where the desired full function buffer was designed for a maximum current taking one pad location with the usual current in the range of twenty four milliamps. The approach followed in CB35000 is to have identical twenty five micron wide output transistor slices stepped around the die. Each slice contains one set of protection diodes to the external power rails and eight P and eight N transistors. The transistors are specifically laid out and selectively non salicided for ESD protection and latch up prevention. These slices are paralleled to meet the current needs of the user, for example, to construct a 24mA sink and 12mA source LVTTL buffer, a number of slices would be used. The next group of devices that makes up the I/O circuits is again 4/16 (R) a 25u wide slice of specialized transistors that are utilized to form the slew rate control sections of the I/O. Each of these slices has circuits to control the switching of up two sections of P and N output transistors. These sections are of course created from the output transistor slice above the slew rate section and can be connected as desired by the designer. Many configurations of circuits can be created to supply the desired results with slew rate slices paralleled with multiple output sections. A further function of the I/O circuits is current spike suppression during switching of the I/O transistors. The logic utilized causes the conducting transistors to turn off before the opposing set of transistors turn on. Figure 3 IO Buffer Technology EDGE OF DIE GUARDRING PROGRAMMABLE PITCH BOND PADS 4mA Selected SEGMENTED OUTPUT RIVER OF DRIVE TRANSISTORS INPUT CONTROL SLEW RATE TRISTATE BUSKEEPER LEVEL SHIFTER DIE CORE CB35000 SERIES MPUL LPUL Vdd + 0.3 Volts 0.8 * Vdd Typical Current from all Vdd supplies at LPUL or MPDL 25 A per receiver 0.2 * Vdd MPDL LPDL Trip Level = 0.5 * Vdd Figure 4a D.C. Specifications for LVCMOS Input Receivers Vss - 0.3 Volts MPUL LPUL Vdd + 0.3 Volts Vss + 2.0 Volts Typical Current from all Vdd supplies at LPUL or MPDL 25 A per receiver MPDL LPDL Trip Level = 1.4 Volts (nominal) Vss + 0.8 Volts Vss - 0.3 Volts Figure 4b D.C. Specifications for LVTTL Input Receivers Table 2 I/O Drive Capacity for LVCMOS and LVTTL Slew Rate Buffers Maximum Capacitance (pF) 50 100 200 300 400 800 Table 3 I/O Drive Capacity for LVCMOS and LVTTL Non Slew Rate Buffers Maximum Capacitance (pF) 50 100 200 300 400 800 5/16 Current Drive (mA) 2.0 4.0 8.0 12.0 16.0 24.0 Current Drive (mA) 2.0 4.0 8.0 12.0 16.0 24.0 (R) CB35000 SERIES Table 4 Temperature (Junction) and Voltage Multipliers KT 0.77 0.83 1.00 1.13 1.17 1.27 KV 1.20 1.11 1.00 0.94 down devices is present in the library. The technologies supported match the output buffer capabilities and include, LVCMOS, LVTTL, GTL, CTL, Differential, etc. and a five volt interface capability. All pads except the sixteen corner pads can be configured as power or I/O pads. The configured power pads are known as placeable pads and have an associated current handling capability. Their placement is dependent on the types of output buffers used in the design. For rules governing the placement of pads, please contact your local SGS-THOMSON design centre. CORE LOGIC The propagation delays shown in the CB35000 data book are given for nominal processing, 3.3V operation, and 25 C temperature conditions. However there are additional factors that affect the delay characteristics of the macrocells. These include loading due to fanout and interconnect routing, voltage supply, junction temperature of the device, processing tolerance and input signal transition time. Prior to physical layout, the design system can estimate the delays associated with any critical path. The impact of the placement and routing can be accurately RC back annotated from the layout for final simulations of critical timing. The effects of junction temperature, (KT) and voltage supply (KV) on the delay numbers are summarized in Table 4. A third factor, is associated with process variation. This multiplier has a minimum of 0.8 and a maximum of 1.2. MACROCELLS AND MACROFUNCTIONS The CB35000 series has internal macrocells that are robust in variety and performance. The cell selection has been driven by the need of Synthesis and HDL based design techniques. This offering is rich in buffers, complex combinatorial cells and multi power drive cells, which allow the Synthesis tool to create a netlist compatible with the requirements of Place and Route tools. Macrofunctions are a series of soft-macros facilitating quick capture of large functional blocks and are available for such functions as counters, Temperature oC -55 -40 25 70 85 125 VDD 2.7 3.0 3.3 3.6 Inside the slew rate sections the next slices of specialized designed components step on a 50 micron wide pattern. The first of these 50 micron wide sections is utilized for predriver circuits; these include specialized built in test functions for the I/O. The predriver of course interfaces the core signals controlling tristate and switching functions with the slew rate and output transistor sections but it also allows all Output Buffers to be driven high, low or put into tristate regardless of the state of the internal logic greatly simplifying parametric testing of the part and also assisting customers who wish to use this feature during board testing. Note that all output buffers can be tristated by this function including buffers that normally do not tristate. This test function also turns off all pull up or down devices and shuts down all differential receivers and converts them into standard CMOS receivers. Inside the predriver is a section of specialized transistors used to create the receiver functions. This section includes specialized non salicide protection resistor diodes to further protect the gates of the receiver devices from ESD and latch up. Also present in this section are devices that can be utilized to form various parameteriseable pull up, pull down and buskeeper functions. A full set of standard receivers with pull up and pull 6/16 (R) CB35000 SERIES Table 5 Module Generator Library Description 256K bits max 16K word max 64 bit max Zero static current, Tristate outputs 128K bits max 8K word max 64 bit max Zero static current, Tristate outputs 2M bits max 32K word max 64 bit max Diffusion programmable, Tristate outputs Parallel asynchronous operation 2's complement product 6 to 64 bits for both inputs Ripple Carry or Fast Carry Look Ahead 100 Mbps serial transputer links coupled with large and fast memory can be used for pipelining, caching and synchro circuits in modern RISC computing architectures. Viterbi and Reed Solomon cores aim at the HDTV and satellite transmission markets. To support telecom needs for CCITT standard applications, ADPCM cells supporting CT2 protocol have been developed. DESIGN FOR TESTABILITY The time and cost for ASIC testing increases exponentially as the complexity and size of the ASIC grows. Using a design for testability methodology allows large, more complex ASICs to be efficiently and economically tested. CB35000 supports the JTAG boundary Scan and both edge and level sensitive scan design techniques by providing the necessary macrocells. Scan testing aids device testability by permitting access to internal nodes without requiring a separate external connection for each node accessed. Testability is assured at device level with the close coupling of LSSD latch elements, Automatic Test Pattern Generation (ATPG) and high pattern depth tester architecture. BIST options for memory generators are also available. At system level, SGS-THOMSON fully supports IEEE 1149.1, and the I/O structure utilized in this family is completely compatible. Several types of 7/16 (R) Cell SPRAM DPRAM ROM MULT shift register and adders. Macrofunctions are implemented at layout by utilizing macrocells and interconnecting to create the logic function. MODULE GENERATORS A series of module generators using compiled cell generation techniques, are available to support a range of megacells. These modules enable the designer to choose individual parameters in order to create a compiled cell, which meets the specific application requirements. These include single port RAM, dual port RAM, ROM and MULT. The compiled cell generators construct custom cells, which are implemented using a special leaf cell technique, ensuring predictable layout and accurate module characteristics. In choosing megacells the designer can consider the trade-offs between speed and area to generate a fully customized cell which meets their specific device requirements. These megacell generators are complemented by a group of application specific embedded megacells. These allow access to technologies that have been hitherto the domain of standard products. Examples include mixed mode cells for graphics, DAC/ADC's (4-9 bit), PLL applications, and Digital Signal Processor functions for cellular comms, fax and high-speed modem.which initially consist of a Triple 8-bit DAC, Graphics RAM, Clock Multiplier PLL and Frequency Synthesis PLL. CB35000 SERIES core scan cells are provided in the CB35000 Series library. Examples include FDxS/FJKxS cells which are edge sensitive and LSxx cells which are true LSSD cells. Non-overlapping clock generator macros are also available. EVALUATION DEVICE An evaluation device is used to demonstrate the performance of the CB35000 series as well as verify the effectiveness of the design system. The device has path delays, latches, a host of macrocells and memory functions which were used to verify the simulated characteristics that are supplied in the data book. Characterization of the path delays including interconnect shows typical delays of 210 ps for a 2 input NAND with receivers/drivers operating at frequencies of 200 MHz. The evaluation device is available in a 208 pin plastic quad flat pack. Figure 5 Evaluation Device 8/16 (R) CB35000 SERIES PACKAGE AVAILABILITY The CB35000 Series is designed to be compatible with QFP, BGA and SBC package types, in addition to the more traditional types found. The options include Plastic Leaded Chip Carriers (PLCC) from 28 to 84 pins, while the Metric Quad Flat Pack (xQFP) offering ranges up to 208 pins. Both high performance and high power variants are available as well as the TQFP thin types. Ball Grid Array (BGA) packages are available from 160 to 500 pins and SBC types allow the pin count to reach the area of 1000 pins. Pin counts for through board mounting (PGA) range up to 480. The diversity in pin count and package style gives the designer the opportunity to find the best compromise for system size, cost and performance requirements. All packages for the military market are hermetically sealed to meet MIL-STD-883 Method. Prototypes are developed in ceramic packages for fast turnaround evaluation. Figure 6 Packaging Capability NUMBER OF LEADS (Pins) 20 28 44 64 68 80 84 100 120 128 144 160 176 180 208 224 225 256 257 304 313 400 480 r A Packages in Production Packages in Development PQFP TQFP PACKAGE NAME BGA PLCC r r r CPGA POWER PQFP Slug/Spreader r r r r r r r r r r r r r r r r r r r r r r r r r r r r r A A A A A A r r r 9/16 (R) CB35000 SERIES DESIGN ENVIRONMENT Several interface levels are possible between SGS-THOMSON and the customer in the undertaking of an ASIC design. The four levels of interface are shown in Figure 7. Level 1 is characterized by SGS-THOMSON receiving the system specification and taking the design through to validation and fabrication. At level 2 interface the designer supplies a complete logic design implemented in a standard generic logic family. SGS-THOMSON then takes the design through to layout, validation and fabrication. Level 3 is the most common and preferred interface level. Logic capture and pre-layout simulation are performed by the designer using an SGS-THOMSON supported design kit. The design is then taken through layout, validation and fabrication by SGS-THOMSON. The SGS-THOMSON design system validates all designs before fabrication. Design kits are provided that allow schematic capture entry via Mentor Graphics and Cadence products. Simulation is supported for Cadence and Mentor Graphics. Full support is also provided for Cadence Verilog, Synopsys VSS and System Hilo simulators. Figure 8 shows the SGSTHOMSON Design Flow. Test vector development uses TSSI software from Summit and Currentest from CrossCheck. Figure 7 Customer/SGS-THOMSON Interface Levels SYSTEM SYSTEM SPECIFICATION LOGIC DESIGN SCHEMATIC CAPTURE DESIGN VERIFICATION PRE-LAYOUT SIMULATION LAYOUT POST-LAYOUT MANUFACTURE SIMULATION AND TEST CUSTOMER SGS-THOMSON INTERFACE LEVELS LEVEL 1 CUSTOMER LEVEL 2 SGS-THOMSON CUSTOMER LEVEL 3 SGS-THOMSON CUSTOMER LEVEL 4 SGS-THOMSON ECR1 ECR2 10/16 (R) CB35000 SERIES Figure 8 SGS-THOMSON Design Flow HARDWARE DESCRIPTION LANGUAGE VHDL / HDL FUNCTIONAL SIMULATION VHDL / HDL LOGIC SYNTHESIS SYNOPSYS SCHEMATIC CAPTURE CADENCE MENTOR GATE LEVEL SIMULATION VERILOG-XL MENTOR SYSTEM HILO VSS FLOORPLANNING DELAY EVALUATION RC BACK ANNOTATION TSSI CURRENTEST CLOCK TREE SYNTHESIS SIGN OFF SIMULATION SGS-THOMSON LAYOUT SILICON 11/16 (R) CB35000 SERIES Table 6 Absolute Maximum Ratings (note1) -0.5 V to +6.0 V -0.5 V to (Vdd + 0.5V) -24mA source, +24mA sink -65 to 150 degrees Centigrade -40 to 125 degrees Centigrade Supply Voltage, Vdd Input or Output Voltage DC Forward Bias Current, Input or Output Storage Temperature Ceramic Storage Temperature Plastic Note 1. Referenced to Vss. Stresses above those listed under "absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect the device reliability. Table 7 Recommended DC Operating Conditions 3.3 V +/- 10% (3.0 V to 3.6 V) 3.3 V + 0.3V/-0.6V (2.7V to 3.6V) Normal Operating Supply Voltage Vdd (note 1) Extended Operating Supply Voltage Vdd (notes 1,2) Operating Ambient Temperature Commercial (note 3) Industrial (note 3) Military (note 4) Note 1. Note 2. Note 3. Note 4. 0 to 70 degrees Centigrade -40 to +85 degrees Centigrade -55 to +125 degrees Centigrade Commercial, Industrial, and Military Conditions Low Voltage TTL Circuits are NOT functional to specifications below 3.0 Volts All circuits will operate to full specifications with a Vdd of 3.0V to 3.6V and a junction temperature of -40 to +125 degrees centigrade. These junction temperatures are compatible with the Commercial and Industrial Temperature Ranges. All circuits will be functional from -55 to +150 degrees centigrade junction temperature (military Ambient Temperature Range) but will not necessary operate to published specifications. Only circuits specified as operational to extended temperature range may be used when operating to Military temperature conditions. Table 8 Special Voltages (Vcc) Operating Conditions 5.0V +/- 10% (4.5 V to 5.5 V) 1.2V +/- 5% (1.14 V to 1.26 V) 1.5V +/- 10% (1.35 V to 1.65 V) FVI (Five Volt Interface) Supply Voltage (notes 1,2) GTL (Gunning Transistor Logic) Supply Voltage (notes 1, 3) CTT (Center Tap Terminated) Supply Voltage (notes 1,4) Note 1. Note 2. Note 3. Note 4. Commercial, and Industrial Use Only -40 +85 degrees Centigrade I/O Circuits Only takes Special External Power Distribution and May NOT be mixed with GTL or CTL circuits on any one side of the die. Only a very limited buffer set is available. I/O Circuits Only takes Special External Power Distribution and May NOT be mixed with FVI or CTL circuits on any one side of the die. Only a very limited buffer set is available. I /O Circuits Only takes Special External Power Distribution and May NOT be mixed with FVI or GTL circuits on any one side of the die. Only a very limited buffer set is available. 12/16 (R) CB35000 SERIES Table 9 Symbol Vil Vih Vol Voh LVTTL Interface DC Electrical Characteristics (Note 1) Parameter Low Level Input Voltage High Level Input Voltage Low Level Output Voltage High Level Output Voltage Iol = Rated Buffer Current Ioh = Rated Buffer Current 2.4 2.0 0.2 3.0 0.4 Conditions Min Typ Max 0.8 Unit Volts Volts Volts Volts Notes 2,3 2,3 2,3,4 2,3,4 Vt + Vt Note 1. Schmitt Trigger +Ve Threshold Schmitt Trigger -Ve Threshold 0.9 1.7 1.1 1.9 Volts Volts 2,3 2,3 Note 2. Note 3. Note 4. These are normal Voltage and extended temperature specifications Vdd from 3.0 V to 3.6 V Temperature Ambient from -55 to 125 degrees Centigrade Adherence to rules in Power Pin / Pad Specifications Required Refer to the CB35000 Standard Cell Specification for full Testing Levels and Conditions Buffers offered in 2, 4, 8, 12, 16, and 24 mA TTL options Table 10 LVCMOS Interface DC Electrical Characteristics (Note 1) Symbol Vil Vih Vol Parameter Low Level Input Voltage High Level Input Voltage Low Level Output Voltage Iol = Rated Buffer Current Ioh = Rated Buffer Current 0.85 x Vdd 0.8 x Vdd 0.2 0.4 Conditions Min Typ Max 0.2xVdd Unit Volts Volts Volts Notes 2,3,4 2,3,4 2,3,4,5,6 Voh High Level Output Voltage 0.9 x Vdd 1.7 1.9 Volts 2,3,4,5,6 Vt + Vt - Schmitt Trigger +Ve Threshold Schmitt Trigger -Ve Threshold 0.9 Volts Volts 2,3 2,3 1.1 Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. These are extended voltage and temperature specifications Vdd from 2.7 V to 3.6 V Temperature Ambient from -55 to 125 degrees Centigrade Adherence to rules in Power Pin / Pad Specifications Required Refer to the CB35000 Standard Cell Specification for full Testing Levels and Conditions Buffers offered in 2, 4, and 8 mA CMOS options Note only one CMOS buffer may sink or source DC current when parametric measurements are taken due to the reason that the power supply specifications for CMOS product are not written to support DC current. If more than one buffer is active voltage drops in the supply may cause false failure readings. If no buffers are sinking or sourcing current and all internal pull up or pull down resistors in bidi buffers have been disabled by having the T2 Test Pin positive Vol (max) = 0.05 Volts and Voh (min)=Vdd-0.05 Volts 13/16 (R) CB35000 SERIES Table 11 General Interface DC Electrical Characteristics (Note 1) Symbol Iil Iih Ioz Cin Co Cio Iklu Vesd Note 1. Parameter Low Level Input Current High Level Input Current Tri-State Output Leakage Input Capacitance Output Capacitance Bidi, I/O Capacitance I/O Latch Up Current Electrostatic Protection Conditions Vi =Vss Vi = Vdd Vo=0V or Vdd Freq=1MHz Freq=1MHz Freq=1MHz V Min Typ Max +/-10 +/-10 +/-10 Unit uA uA uA pF pF pF mA V Notes 2 2 2 3,4 3,4 3,4 2.0 4.0 0.9 200 2000 1.1 500 4000 4.0 5 Note 2. Note 3. Note 4. Note 5. These are extended voltage and temperature specifications Vdd from 2.7 V to 3.6 V Temperature Ambient from -55 to 125 degrees Centigrade Adherence to rules in Power Pin / Pad Specifications Required Excluding Package At 0.0 Volts Human Body Model 14/16 (R) CB35000 SERIES 15/16 (R) DESIGN CENTRES USA Carrollton, TX 75006-5039 1310 Electronics Drive MS 2337 Tel.: (1) 214/466-8844 Lincoln, MA 01773 55 Old Bedford Rd. Tel.: (1) 617/258-0300 San Jose, CA 95110 2055 Gateway Place Suite 300 Tel.: (1) 408/452-8585 EUROPE FRANCE 94253 Gentilly Cedex 7, avenue Gallieni - BP 93 Tel.: (33-1) 47407575 GERMANY 8011 Grasbrunn Bretonischer Ring 4 Neukeferloh Technopark Tel.: (49-89) 460060 ITALY 20090 Assago (MI) Viale Milanofiori Strade 4 - Palazzo A/4/A Tel.: (39-2) 89213215 40033 Casalecchio di Reno (BO) Via R. Fucini, 12 Tel.: (39-51) 591914 SWEDEN S-16421 Kista Borgarfjordsgatan, 13 Box 1094 Tel.: (46-8) 7939220 UNITED KINGDOM and EIRE Marlow, Bucks SL7 1YL Planar House, Parkway Globe Park Tel.: (44-1628) 890800 ASIA/PACIFIC HONG KONG Wanchai 22nd Floor Hopewell Centre 183 Queen's Road East Tel.: (852-5) 8615788 KOREA Seoul 121 8th floor Shinwon Building 823-14, Kuksman-Dong Kang-Nam-Gu Tel.: (82-2) 553-0399 SINGAPORE Singapore 2056 28 Ang Mo Kio Industrial Park 2 Tel.: (65) 482-1411 TAIWAN Taipei 11th Floor 105 Section 2, Tun Hua South Road Tel.: (886-2) 755-4111 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1995 SGS-THOMSON Microelectronics - All rights reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - United Kingdom - U.S.A. |
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